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| INTEGRATED CIRCUITS DATA SHEET TDA8261TW Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer Product specification Supersedes data of 2004 Oct 25 2004 Dec 02 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer FEATURES * Direct conversion Quadrature Phase Shift Keying (QPSK) and 8PSK demodulation (Zero-IF) * 950 to 2175 MHz frequency range * High-level asymmetrical RF input * 0 to 50 dB variable gain on RF input * Loop-controlled 0 to 90 phase shifter * High AGC linearity (<1 dB per bit with an 8-bit DAC), AGC between 0 and 3 V * External baseband filters for In-phase (I) and Quadrature (Q) signal paths * I2C-bus controlled PLL frequency synthesizer * Low phase noise * Operation from a 4 MHz crystal (allowing the use of an SMD crystal) * Five frequency steps from 125 kHz to 2 MHz * Crystal frequency output to drive demodulator IC * Compatible with 5, 3.3 and 2.5 V I2C-bus * Fully compatible and easy to interface with digital satellite demodulators of the Philips Semiconductors family * 5 V DC supply voltage * 32-pin high heat-dissipation package. APPLICATIONS * Direct Broadcasting Satellite (DBS) QPSK demodulation * Digital Video Broadcasting (DVB) QPSK demodulation * BS digital 8PSK demodulation. GENERAL DESCRIPTION The direct conversion QPSK demodulator is the front-end receiver dedicated to digital TV broadcasting, satisfying both DVB and DBS TV standards. The wide range oscillator (from 950 to 2175 MHz) covers the American, European and Asian satellite bands, as well as the Satellite Master Antennae (SMA) TV US standard. The Zero-IF concept discards traditional IF filtering and intermediate conversion techniques. It also simplifies the signal path. TDA8261TW Optimum signal level is guaranteed by gain controlled amplifiers in the RF path. The 0 to 50 dB variable gain is controlled by the signal returned from the Satellite Demodulator and Decoder (SDD) and applied to pin AGCIN. The PLL synthesizer is built on a dual-loop concept. The first loop controls a fully integrated L-band oscillator, using the LC VCO as a reference which runs at a quarter of the synthesized frequency. The second loop controls the tuning voltage of the VCO and improves the phase noise of the carrier within the loop bandwidth. The step size is equal to the comparison frequency. The input of the main divider of the PLL synthesizer is connected internally to the VCO output. The comparison frequency of the second loop is obtained from an oscillator driven by an external 4 MHz crystal. The 4 MHz output available at pin XTOUT may be used to drive the crystal inputs of the SDD, saving an additional crystal in the application. Both the divided and the comparison frequencies of the second loop are compared in a fast phase detector which drives the charge pump. The TDA8261TW includes a loop amplifier with an internal high-voltage transistor to drive an external 33 V tuning voltage. Control data is entered via the I2C-bus. The I2C-bus voltage can be 5, 3.3 or 2.5 V, allowing compatibility with most of the existing microcontrollers. A 5-byte frame is required to address the device and to program the main divider ratio, the reference divider ratio, the charge pump current and the operating mode. A flag is set when the loop is `in-lock'. This flag can be read during read operations, as well as the Power-On Reset (POR) flag. The device has four selectable I2C-bus addresses. The selection is done by applying a specific voltage to pin AS. This feature gives the possibility to use up to four TDA8261TW ICs in the same system. 2004 Dec 02 2 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer Performance summary TDA8261TW performance: * Noise figure at maximum gain = +18 dB * High linearity; IP2 = +19 dBm and IP3 = +14 dBm * Low phase noise on baseband outputs: -78 dBc/Hz (foffset = 1 and 10 kHz; fCOMP = 1 MHz) * 0 to 50 dB variable gain with AGC control * AGC linearity <1 dB/bit with an 8-bit DAC * Maximum I-to-Q amplitude mismatch = 1 dB * Maximum I-to-Q phase mismatch = 3 * Signal rates from 1 to 45 Msymbol/s (depending on the external filter). QUICK REFERENCE DATA SYMBOL VCC ICC Vo(p-p) fosc n PARAMETER supply voltage supply current output voltage (peak-to-peak value) quadrature error oscillator frequency phase noise on baseband outputs CONDITIONS - - - 950 - foffset = 1 and 10 kHz; fCOMP = 1 MHz with appropriate loop filter and charge pump MIN. 4.75 TYP. 5.0 130 750 - - - TDA8261TW System performance, for example, in a tuner application with the TDA8261TW placed after a low-cost discrete LNA: * Noise figure at maximum gain = 8 dB * High linearity; IP2 = 15 dBm and IP3 = 5 dBm * 0 to 50 dB variable gain with AGC control. Specification limitation Please note that this data sheet applies to versions C2 and above only, it does not apply to version C1. For further information, please contact your Philips Semiconductors representative. MAX. 5.25 - - 3 2175 -78 V UNIT mA mV deg MHz dBc/Hz Gv VXTOUT(p-p) dynamic range of voltage gain from pins RFA or RFB to 48 pins IBBOUT or QBBOUT crystal oscillator output voltage on pin XTOUT (peak-to-peak value) ambient temperature T2 = 1; T1 = 0; T0 = 0; driving a load of CL = 10 pF; RL = 1 M 500 50 650 - - dB mV Tamb -20 - +85 C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8261TW HTSSOP32 DESCRIPTION plastic, thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad VERSION SOT549-3 2004 Dec 02 3 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer BLOCK DIAGRAM TDA8261TW handbook, full pagewidth IOUT RFGND2 11 BIASN1 6 BIASN2 18 BBGND1 13 VCC(BB) 15 QBBIN QOUT IBBIN BBGND2 14 19 20 21 12 17 RFA RFB RFGND1 VCC(RF) VCOGND VCC(VCO) 9 10 7 8 22 25 AGC CONTROL 5 16 IBBOUT QBBOUT AGCIN TKA TKB 24 23 VCO FAST PHASE/ FREQUENCY COMPARATOR Q I integrated oscillator DIVIDE-BY-4 15-BIT DIVIDER f DIV XT1 XT2 1 2 OSCILLATOR f XTAL REFERENCE DIVIDER TDA8261TW DIGITAL PHASE COMPARATOR f COMP CHARGE PUMP 33 V AMP 28 CP PLLGND VCC(PLL) 4 3 27 VT 32 31 30 29 26 XTOUT SDA SCL AS BVS I2C-BUS CONTROL LOGIC AND LATCH POWER-ON RESET MBL859 Fig.1 Block diagram. 2004 Dec 02 4 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer PINNING SYMBOL XT1 XT2 VCC(PLL) PLLGND AGCIN BIASN1 RFGND1 VCC(RF) RFA RFB RFGND2 QOUT BBGND1 QBBIN VCC(BB) QBBOUT IBBOUT BIASN2 IBBIN BBGND2 IOUT VCOGND TKB TKA VCC(VCO) BVS VT CP AS SCL SDA XTOUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION 4 MHz crystal oscillator input 1 4 MHz crystal oscillator input 2 supply voltage for PLL circuit (5 V) ground for PLL circuit AGC input from satellite demodulator and decoder RF isolation input 1 (5 V) ground 1 for RF circuit supply voltage for RF stage (5 V) RF signal input A RF signal input B ground 2 for RF circuit quadrature output for external filtering ground 1 for baseband stage quadrature baseband input after external filtering supply voltage for baseband stage (5 V) quadrature baseband output to satellite demodulator and decoder in-phase baseband output to satellite demodulator and decoder RF isolation input 2 (5 V) in-phase baseband input after external filtering ground 2 for baseband stage in-phase output for external filtering ground for VCO circuit VCO tank circuit input B VCO tank circuit input A supply voltage for VCO circuit (5 V) bus voltage select input tuning voltage output for VCO charge pump output address selection input I2C-bus clock input I2C-bus data input and output 4 MHz crystal oscillator output to satellite demodulator and decoder handbook, halfpage TDA8261TW XT1 XT2 VCC(PLL) PLLGND AGCIN BIASN1 RFGND1 VCC(RF) RFA 1 2 3 4 5 6 7 8 32 XTOUT 31 SDA 30 SCL 29 AS 28 CP 27 VT 26 BVS 25 VCC(VCO) 24 TKA 23 TKB 22 VCOGND 21 IOUT 20 BBGND2 19 IBBIN 18 BIASN2 17 IBBOUT MBL855 TDA8261TW 9 RFB 10 RFGND2 11 QOUT 12 BBGND1 13 QBBIN 14 VCC(BB) 15 QBBOUT 16 Fig.2 Pin configuration. 2004 Dec 02 5 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer FUNCTIONAL DESCRIPTION The TDA8261TW contains the core of the RF analog part of a digital satellite receiver. The signal coming from the Low Noise Block (LNB) is coupled through a Low Noise Amplifier (LNA) to the RF inputs. The circuitry in the TDA8261TW performs the Zero-IF quadrature frequency conversion and the two in-phase (IBBOUT) and quadrature (QBBOUT) output signals can be used directly to feed a SDD circuit. The relative phase of I and Q signals is measured on the baseband outputs, when a sine wave unmodulated carrier at flo + 1 MHz is present at the RF input of the TDA8261TW (see Fig.3). TDA8261TW The TDA8261TW has a gain controlled amplifier which is controlled by the SDD. An external VCO tank circuit is connected between pins TKA and TKB. The main elements of the external tank circuit are an SMD coil and a varactor diode. The tuning voltage of 0 to 30 V covers the whole frequency range from 237.5 to 543.75 MHz. The internal loop controls a fully integrated VCO to cover the range 950 to 2175 MHz. The VCO provides both in-phase and quadrature signals to drive the two mixers. The TDA8261TW integrates all elements necessary to control the varactor tuned oscillator except a 4 MHz crystal and a loop filter. It includes a fast phase detector with high comparison frequency to get the lowest phase noise level in the local oscillator. The fDIV output of the15-bit programmable divider passes through the fast phase comparator where it is compared in both phase and frequency with the comparison frequency (fCOMP). fCOMP is derived from the signal present at the pins XT1 and XT2 (fXTAL) divided-down by the reference divider. The buffered XTOUT signal can drive the crystal frequency input of the SDD, saving a crystal in the application. The output of the phase comparator drives the charge pump and loop amplifier section. The loop amplifier includes a high voltage transistor to handle the 30 V tuning voltage at pin VT, this drives a variable capacitance diode in the external circuit of the voltage controlled oscillator. Pin CP is the output of the charge pump. The loop filter is connected between pins CP and VT and the post-filter section is connected between pin VT and the variable capacitance diode. handbook, halfpage output phase MBL864 input spectrum flo output signal fRF = flo +1 MHz frequency channel I channel Q 90 t Fig.3 Relative phase of I and Q signals. For test and alignment purposes, it is possible to release the tuning voltage output and apply an external voltage on pin VT and to select the charge pump function to sink current, source current or to be switched off. 2004 Dec 02 6 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer PROGRAMMING Programming of the TDA8261TW is performed via the I2C-bus. The read or write selection is made with bit R/W (address LSB). The TDA8261TW fulfils the I2C-bus fast mode, according to the Philips I2C-bus specification. I2C-bus voltage The I2C-bus lines SCL and SDA can be connected to an I2C-bus system tied to either 2.5, 3.3 or 5.0 V, that will allow direct connection to most of the existing microcontrollers. The choice of the threshold voltage for the I2C-bus lines is made with pin BVS that needs to be connected to the supply voltage, to ground or needs an open-circuit; see Table 1. Table 1 I2C-bus voltage selection PIN BVS GND Open-circuit VCC Table 2 I2C-bus write data format BYTE Programmable address Programmable Divider 1 (PD1) Programmable Divider 2 (PD2) Control Data 1 (CD1) Control Data 2 (CD2) Notes 1. MSB is transmitted first. 2. X = undefined. 3. Acknowledge bit (A). MSB(1) 1 0 N7 1 C1 1 N14 N6 T2 C0 0 N13 N5 T1 X 0 N12 N4 T0 X BITS(2) 0 N11 N3 R2 X MA1 N10 N2 R1 X I2C-BUS VOLTAGE 2.5 V 3.3 V 5V I2C-bus write mode TDA8261TW I2C-bus write mode: bit R/W = 0; see Table 2. After the transmission of the address (first byte), four data bytes can be sent to fully program the TDA8261TW. The bus transceiver has an auto-increment facility that permits to program the TDA8261TW with a single transmission: one address byte followed by four data bytes (PD1, PD2, CD1 and CD2). The TDA8261TW can be partly programmed provided that the first data byte following the address is PD1 or CD1. The first bit of the first data byte transmitted indicates whether PD1 (first bit = 0) or CD1 (first bit = 1) will follow. Until an I2C-bus STOP condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. Each byte is loaded after the corresponding 8th clock pulse. Programmable divider data (contents of PD1 and PD2) becomes valid only after the 8th clock pulse of PD2, or after a STOP condition if only PD1 needs to be programmed. LSB MA0 N9 N1 R0 X 0 N8 N0 X X ACK(3) A A A A A 2004 Dec 02 7 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer PROGRAMMABLE ADDRESS The programmable address bits MA1 and MA0 offer the possibility of having up to four TDA8260TW devices in the same system. The relationship between the voltage applied on pin AS and the value of bits MA1 and MA0 is given in Table 3. Table 3 I2C-bus address selection VAS 0 to 0.1VCC open-circuit 0.4VCC to 0.6VCC 0.9VCC to VCC MA1 0 0 1 1 MA0 0 1 0 1 Table 5 R2 0 0 0 0 1 1 1 1 OPERATING AND TEST MODES The mode of operation is set using bits T2, T1 and T0 in control byte CD1; see Table 4. Table 4 T2 0 0 0 0 1 1 1 1 Note 1. Status at power-on: the tuning voltage output is released and pin VT is in the high-impedance mode. Mode selection T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 TEST MODE normal operation 1/ TDA8261TW REFERENCE DIVIDER Five reference divider ratios allow to adjust the comparison frequency to different values, depending on the compromise which has to be found between step size and phase noise. The reference divider ratios and the corresponding comparison frequencies are programmed using bits R2, R1 and R0, as described in Table 5. Reference divider ratio R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 DIVIDER RATIO 2 4 8 not allowed not allowed 16 not allowed 32 COMPARISON FREQUENCY 2 MHz 1 MHz 500 kHz not allowed not allowed 250 kHz not allowed 125 kHz PROGRAMMABLE MAIN DIVIDER RATIO Program bytes PD1 and PD2 contain the fifteen bits N14 to N0 that set the main divider ratio. The ratio N = N14 x 214 + N13 x 213 +...+ N1 x 2 + N0. CHARGE PUMP CURRENT Four values of charge pump current can be chosen using bits C1 and C0, according to Table 6. Table 6 C1 0 0 1 1 Typical charge pump current C0 0 1 0 1 ICP (ABSOLUTE VALUE) 420 A 900 A 1320 A 2320 A XTOUT off 1/ POR state = CP sink(1) fXTAL 2 x fDIV 2 x fDIV CP sink normal operation 2 x fref CP off CP source fXTAL fXTAL 2 x fref fXTAL fXTAL 2004 Dec 02 8 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer I2C-bus read mode If bit R/W = 1 the data can be read from the TDA8261TW (see Table 7). After recognition of its slave address, the TDA8261TW generates an acknowledge pulse and transfers the status byte onto the SDA line (MSB first). Data is valid on the SDA line when the SCL clock signal is HIGH. A second data byte can be read from the TDA8261TW if the microcontroller generates an acknowledge on the SDA line. End of transmission will occur if no acknowledge is received from the microcontroller. The TDA8261TW will Table 7 I2C-bus read data format BYTE Address Status byte Notes MSB 1 POR 1 FL(3) 0 X 0 X BITS(1) 0 X MA1 X TDA8261TW then release the data line to allow the microcontroller to generate a STOP condition. The POR flag is set to logic 1 at power-on and when VCC < 2.7 V. It is reset to logic 0 when an end-of-data condition is detected by the TDA8261TW (end of a read sequence). The in-lock flag FL indicates that the loop is phase-locked when set to logic 1. When a read sequence is started, all eight bits of the status byte must be read. LSB MA0 X 1 X ACK(2) A - 1. X can be 1 or 0 and needs to be masked in the microcontrollers' software; MSB is transmitted first. 2. Acknowledge bit (A). 3. FL is valid only in normal mode. POWER-ON RESET At power-on (bit POR = 1) or when the supply voltage drops below 2.7 V, internal registers are set according to Table 8. Table 8 Status at POR BYTE Programmable divider 1 (PD1) Programmable divider 2 (PD2) Control data 1 (CD1) Control data 1 (CD2) Note 1. X = not set. MSB 0 N7 = X 1 C1 = X N14 = X N6 = X T2 = 0 C0 = X N13 = X N5 = X T1 = 0 X BITS(1) N12 = X N4 = X T0 = 1 X N11 = X N3 = X R2 = X X N10 = X N12 = X R1 = X X N9 = X N1 = X R0 = X X LSB N8 = X N0 = X X X 2004 Dec 02 9 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1. SYMBOL VCC Vi PARAMETER supply voltage input voltage pin SDA pin SCL all other pins Vo output voltage pin SDA pin VT all other pins Tamb Tstg Tj tsc Note ambient temperature storage temperature junction temperature short-circuit time each pin short-circuited to VCC or GND CONDITIONS MIN. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -20 -40 - - TDA8261TW MAX. +6.0 +6.0 +6.0 VCC + 0.3 +6.0 +35 VCC + 0.3 +85 +150 150 10 UNIT V V V V V V V C C C s 1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible damages to the TDA8261TW. Maximum ratings cannot be accumulated. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handle integrated circuits. Every pin withstands 2000 V in the ESD test in accordance with "JEDEC Specification EIA/JESD22-A114A", HBM model (category 1c), except for pin 1 (XT1) which withstands 500 V, pin 2 (XT2) which withstands 1000 V and pin 8 (VCC(RF)) which withstands 1500 V. Identically, every pin withstands 200 V in the ESD test in accordance with "JEDEC Specification EIA/JESD22-A115A", MM model (category A). PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 41.4 UNIT K/W 2004 Dec 02 10 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer TDA8261TW CHARACTERISTICS Tamb = 25 C; VCC = 5 V; unless otherwise specified; RL = 1 k on base band output IBBOUT and QBBOUT; Vo(p-p) = 750 mV on IBBOUT and QBBOUT. SYMBOL Supply VCC ICC VPOR LOleak Gv Gv(max) Vo(p-p) IP2i IP3i F Zo Zi Gv(I-Q) supply voltage supply current voltage limit where POR active 4.75 - - - VAGC = 0 to 3 V VAGC = 3 V; see Figs 4 and 5 recommended value at RF input; VAGC = 0 V at RF input; VAGC = 0 V at maximum gain; VAGC = 3 V; see Fig.6 48 55 - - - - - - 5.00 130 2.7 -75 50 57 750 19 14 18 35 1.0 - 5.25 - - - - - - - - - - - 1 V mA V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Performances from pins RFA or RFB to pins IBBOUT or QBBOUT LO leakage through pins RFA and RFB dynamic voltage gain range maximum voltage gain output voltage (peak-to-peak) 2nd-order interception point 3rd-order interception point noise figure output impedance on pin IOUT and QOUT input impedance on pin IBBIN and QBBIN dBm dB dB mV dBm dBm dB k dB voltage gain mismatch between in 22.5 MHz band with - I and Q bypass capacity 100 nF between IOUT and IBBIN, QOUT and QBBIN absolute quadrature error VAGC = 1.5 V; Vo = 750 mV (peak to peak value); measured in baseband - 0 3 deg Pulling sensitivity 3/4LO 5/4LO sensitivity to pulling on the third see Table 9 and Fig.8 harmonic of the external VCO sensitivity to pulling on the fifth harmonic of the external VCO see Table 9 and Fig.8 - - -40 -40 -35 -35 dBc dBc VCO and synthesizer fosc n(osc) n MDR oscillator frequency oscillator phase noise in the satellite band phase noise on baseband outputs main divider ratio foffset = 100 kHz; out of PLL loop bandwidth foffset = 1 and 10 kHz; fCOMP = 1 MHz; see Fig.7 950 - - 64 - -100 - - 2175 -94 -78 32767 MHz dBc/Hz dBc/Hz 2004 Dec 02 11 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer SYMBOL Zosc fxtal Zxtal VXTOUT(p-p) PARAMETER crystal oscillator negative impedance (absolute value) crystal frequency crystal series resistance crystal oscillator output voltage on pin XTOUT (peak-to-peak value) recommended value T2 = 1; T1 = 0; T0 = 0; driving a load of CL = 10 pF; RL = 1 M T2 = 1; T1 = 1; T0 = 0 CONDITIONS MIN. 1.0 - - 500 TYP. 1.5 4 - 650 TDA8261TW MAX. - - 200 - UNIT k MHz mV Charge pump output; pin CP IL IL(off) Vo(VT) leakage current -10 - 0.2 0 - - +10 nA A V Tuning voltage output; pin VT leakage current when switch off T2 = 0; T1 = 0; T0 = 1; Vtune = 33 V output voltage when the loop is locked normal mode; Vtune = 33 V VBVS = VCC VBVS = 0 V VBVS = open VBVS = 0 V VBVS = 5 V VIH HIGH-level input voltage VBVS = open VBVS = 0 V VBVS = 5 V ILIH ILIL fSCL SDA output VACK AS input IIH IIL HIGH-level input current LOW-level input current VAS = VCC VAS = 0 V - -10 - - 10 - A A output voltage during acknowledge Isink = 3 mA - - 0.4 V HIGH-level leakage current LOW-level leakage current SCL input frequency VIH = 5.5 V; VCC = 5.5 V VIH = 5.5 V; VCC = 0 V VIL = 0 V; VCC = 5.5 V 10 32.7 Bus voltage select input; pin BVS ILIH ILIL VIL HIGH-level leakage current LOW-level leakage current - -100 - - - - - - - - 100 - 0.2VCC 0.3VCC - - - 10 10 - 400 A A V V V V V A A A kHz SCL and SDA inputs LOW-level input voltage 0.15VCC V 0.46VCC - 0.35VCC - 0.6VCC - - -10 - - - - - - 2004 Dec 02 12 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer TDA8261TW handbook, halfpage 70 MBL863 handbook, halfpage 60 MBL861 G (dB) G (dB) 60 40 50 20 40 950 0 1150 1350 1550 1750 1950 f (MHz) 2150 0 1 2 VAGC (V) 3 Fig.4 Overall gain as function of frequency response. Fig.5 Overall gain as function of AGC input voltage. MGU798 handbook, halfpage 20 handbook, halfpage -70 MGU796 F (dB) 18 n (dBc/Hz) -80 (1) 16 -90 14 -100 12 (2) 10 950 1150 1350 1550 1750 1950 2150 f (MHz) -110 950 1150 1350 1550 1750 1950 f (MHz) 2150 Fig.6 Noise figure as function of frequency response. Fig.7 Phase noise on I and Q band outputs as function of frequency response. 2004 Dec 02 13 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer TDA8261TW handbook, full pagewidth RF SIGNAL wanted signal GENERATOR ANZAC RF SIGNAL unwanted signal GENERATOR TDA8261TW SPECTRUM ANALYSER MBL860 Fig.8 Measurement method for pulling sensitivity. Table 9 Test signal conditions for pulling measurements SIGNAL FREQUENCY fw = 2161 MHz fuw = 1613 MHz flo = 2150 MHz fw = 1761 MHz fuw = 2188 MHz flo = 1750 MHz -10 dBm -2 dBm - -10 dBm -2 dBm - LEVEL REMARK fw = flo + 11 MHz fuw = flo x 3/4 + 500 kHz - fw = flo + 11 MHz fuw = flo x 5/4 + 500 kHz - 3/4LO test wanted unwanted local oscillator 5/4LO test wanted unwanted local oscillator The level of the wanted and unwanted signal mentioned in the table are measured at the outputs of the RF signal generators. The sensitivity to pulling is measured in baseband by the difference expressed in dB () between the level of the wanted signal and the spurious generated by pulling. The ANZAC reference is HH128. handbook, halfpage Vsignal 11 wanted signal 11.5 spurious signal f (MHz) MGU794 Fig.9 Base band spectrum. 2004 Dec 02 14 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer APPLICATION INFORMATION handbook, full pagewidth 4MHz TDA8261TW C2 39 pF X1 C38 39 pF XT1 XT2 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 XTOUT SDA SCL AS CP VT 4 MHz +5 V VCC(PLL) PLLGND AGCIN BIASN1 RFGND1 C2 C1 12 nF 330 pF R1 4.7 k R10 22 k + 30 V VAGC +5 V BVS VCC(VCO) TKA TKB VCOGND IOUT BBGND2 IBBIN BIASN2 IBBOUT +5 V R3 33 +5 V C21 82 pF L1 18 nH C22 82 pF R5 4.7 k D1 BB178 C3 330 pF R2 1.5 k +5 V C3 RFIN 2.2 pF C10 2.2 pF VCC(RF) RFA RFB RFGND2 QOUT BBGND1 QBBIN TDA8261TW 9 10 11 12 13 14 15 16 HEATSINK 24 23 22 21 20 19 18 17 R4 4.7 k +5 V VCC(BB) QBBOUT MBL858 Fig.10 Typical application. handbook, halfpage R0 35 R2 56 C0 33 pF L1 470 nH C1 82 pF LPF L2 680 nH C3 68 pF C2 100 nF R1 1 k Zout DC coupling Zin MBL856 Fig.11 Typical 36 MHz low-pass filter. 2004 Dec 02 15 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer TDA8261TW andbook, full pagewidth AGCIN 12 14 5 32 1 4 MHz INPUT MATCHING LNA RFA 9 TDA8261TW 2 17 16 21 19 I2C-bus IBBOUT QBBOUT I Q 4 MHz clock PWM TDA10086 MPEG2 TS I2C-bus MBL857 Fig.12 Tuner configuration with a TDA8261TW. Application design The performance of the application using the TDA8261TW strongly depends on the application design itself. Furthermore the printed-circuit board design and the soldering conditions should take into account the exposed die pad underneath the device, as this requires an optimum electrical ground path for electrical performance, together with the capability to dissipate into the application the heat created in the device. Philips Semiconductors can provide support through reference designs and application notes for TDA8261TW together with associated channel decoders. Please contact your local Philips Semiconductors sales office for more information. Wave soldering is not suitable for the TDA8261TW package. This is because the heatsink needs to be soldered to the printed-circuit board underneath the package but with wave soldering the solder cannot penetrate between the printed-circuit board and the heatsink. 2004 Dec 02 16 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer PACKAGE OUTLINE TDA8261TW HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad SOT549-3 D E A X c y exposed die pad side HE vMA Z Dh 32 17 Eh A2 A1 (A3) A pin 1 index L Lp 1 e bp 16 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D (1) 11.1 10.9 Dh 3.65 3.45 E (2) 6.2 6.0 Eh 2.85 2.65 e 0.65 HE 8.3 7.9 L 1 Lp 0.75 0.50 v 0.2 w 0.1 y 0.1 Z 0.78 0.48 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT549-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-01-22 2004 Dec 02 17 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Manual soldering TDA8261TW To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 2004 Dec 02 18 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) TDA8261TW SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. 2004 Dec 02 19 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION TDA8261TW This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Dec 02 20 Philips Semiconductors Product specification Satellite Zero-IF QPSK/8PSK downconverter with PLL synthesizer PURCHASE OF PHILIPS I2C COMPONENTS TDA8261TW Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Dec 02 21 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R25/04/pp22 Date of release: 2004 Dec 02 Document order number: 9397 750 14376 |
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